JEDEC Launches SPHBM4 Standard: AI Chip Memory Cuts Pin Count 75%, Ditches Silicon Interposer, Boosts Speed 4x

According to JEDEC, the international semiconductor standards organization recently unveiled SPHBM4 (JESD330-4), a new high-bandwidth memory standard designed to lower AI chip packaging costs. The standard reduces interface pins by 75% to 512-bit width versus traditional HBM4's 2,048 pins, while quadrupling per-pin signaling speed from 11Gbps to 44Gbps. At 46GT/s, the theoretical peak bandwidth reaches 2.944TB/s with support for 4 to 16 DRAM stacks and maximum capacity of 64GB per package.

Unlike HBM4, which requires expensive silicon interposers and advanced packaging like TSMC's CoWoS, SPHBM4 mounts directly on low-cost standard organic substrates, eliminating dependency on cutting-edge packaging processes and significantly reducing cost barriers.